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Freescale Semiconductor Technical Data
Document Number: MMA6222EG Rev 1, 10/2008
Digital Dual Axis Micromachined Accelerometer
The MMA62XXEG is a two-axis member of Freescale's family of SPI-compatible accelerometers. These devices incorporate digital signal processing for filtering, trim and data formatting. Features * * * * * * * * * * * * * Available in 20/20g, 50/50g, or 100/100g versions. Additional g-ranges between 20 and 100g may be available upon request Full-scale range is independently specified for each axis 400 Hz low-pass filter, 0.1 Hz high-pass filter, 4-pole, 16 s sample time, additional filter options are available Ratiometric analog voltage output 10-bit digital signed data output SPI-compatible serial interface Capture/hold input for system-wide synchronization support 3.3 or 5 V single supply operation On-chip temperature sensor and voltage regulator Bidirectional internal self-test Minimal external component requirements Pb-free 20-pin SOIC package Automotive AEC-Q100 qualified
MMA6222EG MMA6255EG MMA621010EG
2-AXIS SPI-COMPATIBLE ACCELEROMETER
EG SUFFIX (Pb-free) 20-LEAD SOIC CASE 475A-02
PIN CONNECTIONS
N/C N/C XOUT VSSA YOUT CAP/HOLD DIN VPP CREG CS/RESET 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 N/C N/C CREGA CREGA CREF CREF VCC VSS DOUT SCLK
Typical Applications * * * Crash detection (Airbag) Impact and vibration monitoring Shock detection
20-PIN SOIC PACKAGE N/C: NO INTERNAL CONNECTION
ORDERING INFORMATION
Device Name MMA6222EG MMA6222EGR2 MMA6255EG MMA6255EGR2 MMA621010EG MMA621010EGR2 X-Axis g-Level Y-Axis g-Level 20 20 50 50 100 100 20 20 50 50 100 100 Temperature Range -40 to +105C -40 to +105C -40 to +105C -40 to +105C -40 to +105C -40 to +105C Package 475A-02 475A-02 475A-02 475A-02 475A-02 475A-02 Packaging Tubes Tape & Reel Tubes Tape & Reel Tubes Tape & Reel
(c) Freescale Semiconductor, Inc., 2008. All rights reserved.
VCC
VCC CREG CREGA CREF
100 nF 1 F 1 F 100 nF
CS SCLK DI DO
CS_A SCLK1 MOSI1 MISO1
CS_D SCLK2 MOSI2 MISO2
CS SCLK DI DO
MMA62XXEG
VSSA VSS VPP/TEST XOUT YOUT
Main MCU Deployment IC ADC
Safing Sensor(s)
Filter / Comparator
DEPLOY_EN1 DEPLOY_EN2
Note: If one axis of the MMA62XXEG sensor is expected to be used as a confirmation of the other axis, Freescale recommends that MMA62XXEG used in conjunction with an additional sensing/safing device for each axis.
Figure 1-1 Simplified Airbag Application Diagram
1.1
INTRODUCTION
The MMA62XXEG is intended for applications which utilize serial communications as the primary data transfer mechanism. In addition, an analog output with lower accuracy is available. Device serial number, acceleration range, filter characteristics and status information are available along with acceleration data via the SPI interface. A pair of digital-to-analog converters is enabled to provide ratiometric voltage outputs in addition to the digital acceleration value accessible via the SPI.
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1.2
BLOCK DIAGRAM
A block diagram illustrating the major components of the design is shown in Figure 1-2.
VPP VCC CREG CREGA CREGA CREF CREF VSS VSSA CONTROL LOGIC SPI DIN DOUT SCLK CS CAP/HOLD VOLTAGE REGULATOR
UNIT PROGRAMMABLE DATA ARRAY
REFERENCE OSCILLATOR PRIMARY OSCILLATOR
CLOCK MONITOR INTERNAL CLOCK
g-CELL (Y)
SD CONVERTER
SINC FILTER Y IN
CONTROL IN
STATUS OUT DIGITAL OUT
SELF-TEST INTERFACE
TEMP. SENSOR
TEMP
DSP (SEE FIGURE 1-2)
Y OUT
DAC
YOUT
X IN X OUT g-CELL (X) SD CONVERTER SINC FILTER DAC XOUT
Figure 1-2 MMA62XXEG Block Diagram
CONTROL IN OFFSET MONITOR
DSP CONTROL
OUT
Y IN X IN
LOW-PASS FILTER
OFFSET, GAIN, LINEARITY ADJUST
HIGH-PASS FILTER
OUTPUT SCALING OUTPUT SCALING
DIGITAL OUT TO Y DAC TO X DAC
TEMP
Figure 1-3 MMA62XXEG DSP Block Diagram NOTE: Models of signal chain are available upon request.
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1.3
PIN FUNCTIONS
The pinout for the MMA62XXEG device is illustrated in Figure 1-4. Pin functions are described below. When self-test is active, the output becomes more positive in both axes if ST1 is cleared, or more negative in both axes if ST1 is set, as described in Section 3.1.1.
N/C N/C XOUT VSSA YOUT CAP/HOLD DIN VPP CREG CS/RESET
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
N/C N/C CREGA CREGA CREF CREF VCC VSS DOUT SCLK
20-PIN SOIC PACKAGE N/C: NO INTERNAL CONNECTION
X: +1g Y: 0g
X: 0g Y: +1g
X: 0g Y: -1g
TO CENTER OF GRAVITATION FIELD
X: -1g Y: 0g Response to static orientation within 1g field.
Figure 1-4 MMA62XXEG Pinout
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1.4
1.4.1
PIN FUNCTION DESCRIPTIONS
VCC
This pin supplies power to the device. Careful printed wiring board layout and capacitor placement is critical to ensure best performance. An external bypass capacitor between this pin and VSS is required, as described in Section 1.5.
1.4.2
VSS VSSA
This pin is the power supply return node for the digital circuitry on the MMA62XXEG device.
1.4.3
This pin is the power supply return node for analog circuitry on the MMA62XXAEG device. An external bypass capacitor between this pin and VCC is required, as described in Section 1.5.
1.4.4
CREG
This pin is connected to the internal digital circuitry power supply rail. An external filter capacitor must be connected between this pin and VSS, as described in Section 1.5.
1.4.5
CREGA
These pins are connected in parallel to the internal analog circuitry power supply rail. One or two external filter capacitors must be connected between these pins and VSSA, as described in Section 1.5. Two pins are provided to support redundant connection to the printed wiring board assembly. Redundant external capacitors may be connected to these pins for maximum reliability, as described in Section 1.5.
1.4.6
CREF
These pins are connected in parallel to an internal reference voltage node utilized by the analog circuitry. One or two external filter capacitors must be connected between these pins and VSSA, as described shown in Section 1.5. Two pins are provided to support redundant connection to the printed wiring board assembly. Redundant external capacitors may be connected to these pins for maximum reliability, as described in Section 1.5.
1.4.7
VPP
This pin should be tied directly to VSS.
1.4.8
SCLK
This input pin provides the serial clock to the SPI port. The state of this pin is also used as a qualifier for externally-controlled reset. An internal pull-down device is connected to this pin. This input may be left unconnected unless it is desired to initiate device reset as described in Section 1.4.9.
1.4.9
CS/RESET
This pin provides two functions. When the SPI is enabled, this pin functions as the chip select input for the SPI port. The state of the DIN pin during low-to-high transitions of SCLK is latched internally and DOUT is enabled when CS is at a logic low level. This pin may also be used to initiate a hardware reset. If CS is held low and SCLK is held high for 512 s, the internal reset signal is asserted. An internal pull-up device is connected to this pin.
1.4.10
DOUT
This pin functions as the serial data output for the SPI port. Immediately following device reset, DOUT is placed in a high impedance state for approximately 800 s. At the end of this time, DOUT is driven high and a 3ms stabilization delay required by the internal circuitry begins. Reset is reported by the device so the system can be aware of potential difficulties if unexpected resets occur.
1.4.11
DIN
This pin functions as the serial data input to the SPI.
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1.4.12
CAP/HOLD
When this input pin is low, the SPI acceleration result registers are updated by the DSP whenever a data sample becomes available. Upon a low-to-high transition of CAP/HOLD, the contents of the acceleration result registers are frozen. The result registers will not be updated so long as this pin remains at a logic `1' level. This pin may be tied directly to VSS if the hold function is not desired.
1.4.13
XOUT, YOUT
Two Digital-to-Analog Converters (DACs) translate output of the DSP block into voltage levels proportional to the magnitude of the numerical result and ratiometric to VCC. The DAC outputs have an inherent accuracy of about 12%.
1.5
EXTERNAL COMPONENTS
The connections illustrated below are recommended. Careful printed wiring board layout and component placement is essential for best performance. Low ESR capacitors must be connected to CREG and CREGA pins for the best performance. A grounded land area with solder mask should be placed under the package for improved shielding of the device from external effects. If a land area is not provided, no signals should be routed beneath the package. See Figure 1-1.
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SECTION 2 PERFORMANCE SPECIFICATION
2.1 MAXIMUM RATINGS
Maximum ratings are the extreme limits to which the device can be exposed without permanently damaging it. The device contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table below. Keep input and output voltages within the range VSS V VCC.
Ref 1 Supply Voltage 2 CREG, CREGA, CREF 3 VPP 4 SCLK, CS, DIN, CAP/HOLD 5 DOUT (high impedance state) 6 Current Drain per Pin Excluding VCC and VSS 7 Acceleration (without hitting internal g-cell stops) 8 Powered Shock (six sides, 0.5 ms duration) 9 Unpowered Shock (six sides, 0.5 ms duration) 10 Drop Shock (to concrete surface) 11 12 13 Electrostatic Discharge Human Body Model (HBM) Charge Device Model (CDM) Machine Model (MM) Rating Symbol VCC VREG VREG VIN VIN I gmax gpms gshock hDROP VESD VESD VESD Tstg Value -0.3 to +7 -0.3 to +3 -0.3 to +11 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 10 800 1500 2000 1.2 2000 500 200 -40 to +125 Unit V V V V V mA g g g m V V V C (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1)
14 Storage Temperature Range Notes: 1. Verified by characterization, not tested in production.
2.2
OPERATING RANGE
The operating ratings are the limits normally expected in the application and define the range of operation.
Ref 16 17 18 Characteristic Supply Voltage Standard Operating Voltage, 3.3V operating range Standard Operating Voltage, 5V operating range Operating Temperature Range TA Symbol VCC VCC Min VL +3.15 +4.75 TL -40 Typ +3.3 +5.0 Max VH +3.45 +5.25 TH +105 Units V V C (1) (1) (2)
Notes: 1. Characterized at all values of VL and VH. Production test is conducted at typical voltage unless otherwise noted. 2. Parameters tested 100% at final test.
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2.3
ELECTRICAL CHARACTERISTICS
VL (VCC - VSS) VH, TL TA TH, |TA| < 4 K/min unless otherwise specified
Ref 19 20 21 22 23 Characteristic Supply Current Drain VCC = 5.25 V, tS = 16 s Power-On Recovery Threshold (See Figure 2-1) VCC CREG CREGA CREF Power-On Reset Threshold (See Figure 2-1) VCC CREG CREGA CREF Hysteresis (VPOR_N - VPOR_A, See Figure 2-1) VCC CREG CREGA CREF # Symbol IDD VPOR_N VPOR_N VPOR_N VPOR_N Min 2.77 1.80 2.18 1.11 Typ Max 9.5 3.15 2.32 2.50 1.29 Units mA V V V V (2) (2) (2) (2) (2) (2) (2) (2) (2)
24 25 26 27
VPOR_A VPOR_A VPOR_A VPOR_A
2.77 1.80 2.18 1.11

2.95 2.10 2.31 1.19
V V V V
28 29 30 31
VHYST VHYST VHYST VHYST VDACU VDD V2.5 VREF
0 0 0 0 2.42 2.42 1.20
2.50 2.50 1.25
388 300 261 150 2.0 2.58 2.58 1.29
mV mV mV mV V V V V (2) (1) (1) (1)
32 Minimum Functional Voltage (See Figure 2-1) 33 34 35 Internally Regulated Voltages CREG CREGA (3) CREF External Filter Capacitor (CREG, CREGA) Value ESR (including interconnect resistance) Power Supply Coupling (4) Digital output Analog output
* *
36 37
CREG ESR
800
1000
200
nF m
(2) (2)
38 39
0.004
digit/mv
See Figure 2-2 * * * * * * SENS SENS SENS SENS SENS SENS -4 -4 0.04097 0.0717 0.1024 0.2048 +4 +4 g/digit g/digit g/digit g/digit % %
(2) (2)
Digital Sensitivity (DOUT) 20 g Range 35 g Range 50 g Range 100 g Range Sensitivity Error TA = 25C 44 45 -40C TA 105C 40 41 42 43 Notes: 1. 2. 3. 4. 5. (#) (*)
(1)(5) (1)(5) (1)(5) (1)(5) (1)(5) (1)(5)
Parameters tested 100% at final test. Verified by characterization, not tested in production. Tested at VCC = VL and VCC = VH. Power supply ripple at frequencies greater than 900 kHz should be minimized to the greatest extent possible. Devices are trimmed at 100 Hz with 1000 Hz low pass filter selected. Indicates a FSL significant parameter (CPK > 1.33). Indicates a FSL critical parameter (CPK > 1.67).
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2.3
ELECTRICAL CHARACTERISTICS (CONTINUED)
VL (VCC - VSS) VH, TL TA TH, |TA| < 4 K/min unless otherwise specified
Ref 46 47 48 49 Characteristic * * * * * * * * Symbol ASENS ASENS ASENS ASENS SENS SENS DOUT AOUT RANGE OFS ORS URS UFS UNUSED UNUSED gOVER gOVER gOVER gOVER Min -16 -16 -40 0.44 x VCC -509 -- -- -- -- Typ 23.4 13.40 9.37 4.68. 0 0.5 x VCC -- 510 509 -510 -511 511 -512 +20.9 +36.6 +52.1 +104.3 Max +16 +16 +40 0.56 x VCC 508 -- -- -- -- Units mV/V/g mV/V/g mV/V/g mV/V/g % % digit V digit digit digit digit digit digit digit g g g g (1) (1) (1) (1) (1) (1) (1) (1) (5) (5) (5) (5) (5) (5) (5) (2) (2)
Analog Sensitivity (XOUT, YOUT) 20 g Range 35 g Range 50 g Range 100 g Range Sensitivity Error TA = 25C 50 51 -40C TA 105C 52 53 54 55 56 57 58 59 60 61 62 63 64 Offset at 0 g (High-pass filter disabled) 10-bits, signed Analog output trimmed for digital operation Range of Output (DOUT, 10 bits, signed) Normal Positive Acceleration Overflow Code Positive Acceleration Overrange Code Negative Acceleration Underrange Code Negative Acceleration Underlfow Code Unused Code Unused Code Output value on overrange 20 g Range 35 g Range 50 g Range 100 g Range Output value on underrange 20 g Range 35 g Range 50 g Range 100 g Range
+20.0 +35.0 +50.0 +100.1
+22.1 +38.7 +55.3 +110.5
65 66 67 68
gUNDER gUNDER gUNDER gUNDER
-20.1 -35.1 -50.0 -100.1
-20.9 -36.6 -52.2 -104.5
-22.2 -38.8 -55.4 -110.7
g g g g
Maximum acceleration without saturation of internal circuitry All ranges 69 70 Nonlinearity 71 Noise (1Hz-1kHz) Positive Self Test Output Change (DOUT, digital) TA = 25C -40C TA 105C (XOUT, YOUT, analog) TA = 25C -40C TA 105C Parameters tested 100% at final test. Verified by characterization, not tested in production. Functionality verified 100% via scan. Indicates a FSL critical parameter (CPK > 1.67).
gSAT NLOUT nSD
-200 -1 --
-- -- --
+200 1 1.1
g % FSR mg/Hz
(2) (2) (2)
72 73 74 75
* * * *
ST ST ST ST
67 62 10 10
72 72 -- --
77 82 18 18
digit digit % FS % FS
(1) (1) (1) (1)
Notes: 1. 2. 5. (*)
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2.3
ELECTRICAL CHARACTERISTICS (CONTINUED) VL (VCC - VSS) VH, TL TA TH, |TA| < 4 K/min unless otherwise specified
Ref Characteristic Negative Self Test Output Change (DOUT, digital) TA = 25C -40C TA 105C (XOUT, YOUT, analog) TA = 25C -40C TA 105C Cross-Axis Sensitivity VZX VYX VZY VXY Symbol Min Typ Max Units
76 77 78 79 80 81 82 83 84 85 86 87 88
ST ST ST ST VZX VYX VZY VXY AVLOW AVHIGH OFST GERR DNL INL INL
-78 -82 -18 -18 -4 -4 -4 -4 -- VCC - 0.25 -0.2 -0.3 -2 -3 -3.5
-72 -72 -- -- -- -- -- -- -- -- -- -- -- --
-66 -62 -10 -10 +4 +4 +4 +4 0.25 -- +0.2 +0.3 +2 +3 +3.5
digit digit % FS % FS % % % % V V %FSR %FSR digit digit digit
(6) (6) (6) (6) (6) (6) (6) (6) (2) (2) (2) (2) (2) (2) (6)
DAC Characteristics (XOUT, YOUT) Minimum Output Level, IOUT = -200 A Maximum Output Level, IOUT = 200 A Offset Error Gain Error Differential Nonlinearity Integral Nonlinearity 89 TA = 25C 90 -40C TA 105C Output High Voltage DOUT (ILoad = -100 A) 91 3.15 V (VCC - VSS) 3.45 V 92 4.75 V (VCC - VSS) 5.25 V Output Low Voltage DOUT, (ILoad = 100 A) 93 3.15 V (VCC - VSS) 3.45 V 94 4.75 V (VCC - VSS) 5.25 V 95 96 97 98 Output Loading (DOUT) Load Resistance Load Capacitance Output Loading (XOUT, YOUT) Load Resistance Load Capacitance
VOH VOH
3.25 3.75
-- --
-- --
V V
(2) (2)
VOL VOL ZOUT COUT ZOUT COUT
-- -- 47 -- 25 --
-- -- -- -- -- --
0.4 0.4 -- 35 -- 60
V V k pF k pF
(2) (2) (6) (6) (6) (6)
Input High Voltage CS/RESET, SCLK, DIN/ST, CAP/HOLD 99 3.15 V (VCC - VSS) 3.45 V 100 4.75 V (VCC - VSS) 5.25 V Input Low Voltage CS/RESET, SCLK, DIN/ST, CAP/HOLD 101 3.15 V (VCC - VSS) 3.45 V 102 4.75 V (VCC - VSS) 5.25 V Input Current High (at VIH) SCLK, DIN, CAP/HOLD 103 104 VPP/TEST (internal pulldown resistor) Low (at VIL) 105 CS/RESET Notes: 1. Parameters tested 100% at final test. 2. Verified by characterization, not tested in production. 6. Parameters tested 100% at unit probe.
VIH VIH
1.5 2.5
-- --
-- --
V V
(2) (2)
VIL VIL
-- --
-- --
0.85 1.0
V V
(2) (2)
IIH RIN IIL
-30 190 30
-50 270 50
-260 350 260
A k A
(2) (2) (2)
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2.4
CONTROL TIMING
VL (VCC - VSS) VH, TL TA TH, |TA| < 4 K/min unless otherwise specified
Ref Characteristic Symbol Min 380 335 fC(HPF) OHPF tOP tXY fOSC fMON tCSRES tSCLK tCSCLK tDC tCDIN tCDOUT tCHCSH tCSN fC BWGCELL 0.095 -- -- -- 3.8 3.6 486 120 60 20 10 -- 60 526 5 -- Typ 400 353 0.1 1 -- -- 4.0 -- 512 -- -- -- -- -- -- -- 10 3 Max 420 371 0.105 -- 840 10 4.2 4.4 538 -- -- -- -- 50 -- -- 20 -- Units Hz Hz Hz 1 s ms MHz MHz s ns ns ns ns ns ns ns kHz kHz (1) (1) (1) (1) (1) (2) (3) (1) (1) (1) (1) (1) (1) (1) (1) (1) (4) (2)
DSP Low-Pass Filter (5) Cutoff frequency (6) 106 DSP Low-Pass Filter Cutoff frequency (-3dB, referenced to 0 Hz) 107 108 109 110 111 DSP High-Pass Filter Cutoff frequency Filter Order Power-On Recovery Time POR negated to CS low Power applied to XOUT, YOUT valid
112 Internal Oscillator Frequency 113 Clock Monitor Threshold 114 Chip Select to Internal Reset (See Figure 2-3) 115 116 117 118 119 120 121 122 Serial Interface Timing (See Figure 2-4) Clock period CS asserted to SCLK high Data setup time Data hold time SCLK low to data out SCLK high to CS negated CS negated to CS asserted DAC Low-Pass Filter Cutoff Frequency
123 Sensing Element Rolloff Frequency (-3 dB) Notes: 1. 2. 3. 4. 5. 6.
Functionality verified 100% via scan. Timing characteristic is directly determined by internal oscillator frequency. Verified by characterization, not tested in production. Parameters tested 100% at final test. Parameters tested 100% at unit probe. Devices are trimmed at 100 Hz with 1000 Hz low-pass filter option selected. Cutoff frequencies shown are -4dB referenced to 0 Hz response, to correspond with previous specifications.
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5.5V VPOR_N VDACU VPOR_A
VCC
POR tXY XOUT/YOUT
DAC OUTPUT UNCERTAIN Figure 2-1 Power-Up Timing
Figure 2-2 Power Supply Coupling - DAC Outputs
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CS tCSRES INTERNAL RESET
SCLK
Figure 2-3 CS Reset Timing
CS tCSN tCSCLK SCLK tDC DIN tCDOUT DOUT
Figure 2-4 Serial Interface Timing
tSCLK
tCHCSH
tCDIN
DATA VALID
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SECTION 3 INTERNAL MODULES
3.1 ONE-TIME PROGRAMMABLE DATA ARRAY
A 400-bit programmable data array allows each device to be customized. The array interface incorporates parity circuitry for fault detection along with a locking mechanism to prevent unintended changes. Portions of the array are reserved for factory-programmed trim values. Customer accessible data stored in the array are shown in the table below. Addresses $00 - $0D are associated with the programmable data array. A writable register at address $0E is provided for device control operations. Two read-only registers at addresses $0F and $10 provide status information. Unused bits within the data array are always read as `0' values. Unprogrammed OTP bits are also read as `0' values. Table 3-1 Customer Accessible Data
Location Address $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0E $0D $0F $10 $11 DEVCTL DSPCFG TEMP DEVSTAT COUNT RES_1 SPARE TEMP[7] IDE COUNT[7] RES_0 SPARE TEMP[6] OSCF COUNT[6] CE INTERP TEMP[5] DEVINIT COUNT[5] Register SN0 SN1 SN2 SN3 DEVCFG0 DEVCFG1 DEVCFG2 DEVCFG3 DEVCFG4 DEVCFG5 AXCFG_X AXCFG_Y LOCK2 RNG_X[2] RNG_Y[2] PAR2 RNG_X[1] RNG_Y[1] COMP1 RNG_X[0] RNG_Y[0] 7 SN[7] SN[15] SN[23] SN[31] 6 SN[6] SN[14] SN[22] SN[30] 5 SN[5] SN[13] SN[21] SN[29] Bit Function Type 4 SN[4] SN[12] SN[20] SN[28] 3 SN[3] SN[11] SN[19] SN[27] 2 SN[2] SN[10] SN[18] SN[26] 1 SN[1] SN[9] SN[17] SN[25] 0 SN[0] SN[8] SN[16] SN[24]
Factory Programmed Factory Programmed F Factory Programmed Factory Programmed Factory Programmed COMP0 LPF_X[4] LPF_Y[4] Unused Reserved OVLD TEMP[4] TF COUNT[4] HPFB SD TEMP[3] HPF COUNT[3] YINV HPFD TEMP[2] OFF_Y COUNT[2] ST1 HPFSEL TEMP[1] OFF_X COUNT[1] ST0 OFMON TEMP[0] DEVRES COUNT[0] R SPARE LPF_X[3] LPF_Y[3] DACEN LPF_X[2] LPF_Y[2] AD3 LPF_X[1] LPF_Y[1] AD2 LPF_X[0] LPF_Y[0] N/A R/W F
Type codes F: Factory programmed OTP location R: Read-only register R/W: Read/write register N/A: Not applicable
3.1.1
`DEVICE CONTROL REGISTER (DEVCTL)
A read-write register at address $0E supports a number of device control operations as described below. Reserved bits within DEVCTL are always read as logic `0' values. Table 3-2 Device Control Register
Bit Address $0E Register 7 DEVCTL RES1 6 RES0 5 CE 4 Reserved 3 HPFB 2 YINV 1 ST1 0 ST0
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3.1.1.1
Reset Control (RES_1, RES_0)
A specific series of three write operations involving these two bits will cause the internal digital circuitry to be reset. The state of the remaining bits in the DEVCTL register do not affect the reset sequence, however any write operation involving this register in which both RES_1 and RES_0 are cleared will terminate the sequence. To reset the internal digital circuitry, the following register write operations must be performed in the order shown: 1. Set RES1. RES0 must remain cleared. 2. Set RES1 and RES0. 3. Clear RES1 and set RES0. RES1 and RES0 are always read as logic `0' values. After reset sequence has been completed DEVCTL register will read 0X00. It should be noted that after a reset or power-cycle sequence is completed the DEVCTL register reset to the value 0X00. 3.1.1.2 Clear Error (CE)
Setting this bit to a logic `1' state will clear transient error status conditions. It is necessary to either set this bit or perform a device reset if an error condition has been reported by the device before acceleration data transfer can be resumed. The device reset condition may be cleared only after device initialization has completed. Error conditions and classification are described in Section 4.2. The state of this bit is always read as logic `0'. 3.1.1.3 High-Pass Filter Bypass (HPFB)
Setting this bit will remove the high-pass filter from the signal chain within the DSP block. The state of this bit is indicated when DEVCTL is read. This bit is always cleared following reset. The state of the high-pass filter is frozen when this bit is at a logic `1' level. 3.1.1.4 Self-Test Control (ST1, ST0)
Bidirectional self-test control is provided through manipulation of these bits. ST1 controls direction while ST0 enables and disables the self-test circuitry. ST1 and ST0 are always cleared following internal reset. When ST0 is set, the high-pass filter is bypassed and the values within the high-pass filter are frozen. Both axes are affected simultaneously by the state of these bits. If the offset monitor is enabled, self-test activation in a single direction should be limited to less than 30 ms. The state of the ST0 bit is indicated as part of all acceleration results. 3.1.1.5 Y-Axis Signal Inversion Control (YINV)
This control function is provided as a means to verify operation of the two-channel multiplexor which alternately provides X-axis and Y-axis data to the DSP. An inverter block and multiplexor at the Y-axis input to the DSP are controlled by the YINV bit. Setting this bit when ST0 is set has the effect of changing the sign of acceleration in the Y-axis. Operation of the YINV bit is illustrated in Figure 3-1 below. Y-axis inversion may be selected only during self-test; the state of this bit has no effect when ST0 is cleared.
ST0 YINV DSP
1
Y CONVERTER
SINC FILTER
0
X CONVERTER
SINC FILTER
Figure 3-1 Y-Axis Inversion Function
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Self-test operations controlled by YINV along with ST1 and ST0 are summarized in the following table. Table 3-3 Self-Test Control Operations
Self-Test Operation YINV X 0 0 1 1 ST1 X 0 1 0 1 ST0 X-Axis 0 1 1 1 1 Y-Axis Self Test Disabled, Y-Axis Signal Inversion Disabled Positive Deflection Negative Deflection Positive Deflection Negative Deflection Negative Deflection Positive Deflection
NOTE: Offset correction is applied within the DSP, and is not affected by the state of the YINV bit. Consequently, inversion of the Y-axis signal may result in saturation of the Y-axis output value.
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Correct operation of the DSP input multiplexor may be confirmed by performing the operations shown in Figure 3-2.
YINV = 0, ST1 = 0, ST0 = 1 READ ACCELERATION (R1) YINV = 0, ST1 = 1, ST0 = 1 READ ACCELERATION (R2)
YINV = 0, ST1 = 0, ST0 = 1 READ ACCELERATION (R1) YINV = 0, ST1 = 1, ST0 = 1 READ ACCELERATION (R2)
R1 > R2
N
R1 > R2
N
Y
Y
YINV = 1, ST1 = 0, ST0 = 1 READ ACCELERATION (R3) YINV = 1, ST1 = 1, ST0 = 1 READ ACCELERATION (R4)
YINV = 1, ST1 = 0, ST0 = 1 READ ACCELERATION (R3) YINV = 1, ST1 = 1, ST0 = 1 READ ACCELERATION (R4)
R3 R4
N
R3 R4
N
Y
Y
MULTIPLEXOR VERIFICATION SUCCESSFUL
MULTIPLEXOR VERIFICATION FAILED
MULTIPLEXOR VERIFICATION SUCCESSFUL
MULTIPLEXOR VERIFICATION FAILED
X-axis
Figure 3-2 DSP Input Multiplexor Verification Flow Chart
Y-axis
3.1.2
Temperature Sensor Value (TEMP)
This read-only register contains a signed value which provides a relative temperature indication. The temperature sensor is uncalibrated and its output for a given temperature will vary from one device to the next. The value in this register increases with temperature. Table 3-4 Temperature Sensor Value Register
Location Address $0F Register TEMP 7 TEMP[7] 6 TEMP[6] 5 TEMP[5] Bit Function 4 TEMP[4] 3 TEMP[3] 2 TEMP[2] 1 TEMP[1] 0 TEMP[0]
3.1.3
Device Status Register (DEVSTAT)
This read-only register is accessible in all modes. Table 3-5 Device Status Register
Location Address $10 Register DEVSTAT 7 IDE 6 OSCF 5 DEVINIT Bit Function 4 TF 3 HPF 2 OFF_Y 1 OFF_X 0 DEVRES
3.1.3.1
Internal Data Error Flag (IDE)
This flag will be set if a register data parity fault or a marginally programmed fuse is detected. Device reset is required to clear this fault condition. If a parity error is associated with the data stored in the fuse array, this fault condition cannot be cleared. This flag is disabled when the device is in test mode. MMA6222EG Sensors Freescale Semiconductor 17
3.1.3.2
Oscillator Fault Flag (OCSF)
This flag will be set if the primary oscillator and reference oscillator frequencies vary by an amount greater than the specified tolerance. In normal operating mode, an oscillator fault condition will result in DOUT being driven high when CS is asserted. 3.1.3.3 Device Initialization Flag (DEVINIT)
This flag is set during the interval between negation of internal reset and completion of device initialization. DEVINIT is cleared automatically. 3.1.3.4 Temperature Fault Flag (TF)
This flag is set if the value reported by the on-chip temperature sensor exceeds specified limits. TF may be cleared by writing a logic `1' value to the CE bit in DEVCTL, provided that the fault condition is no longer detected. 3.1.3.5 High-Pass Filter Status (HPF)
This bit is set when a high-pass filter is present in the DSP signal chain when the HPFB bit has been set. 3.1.3.6 3.1.3.7 Y-Axis Offset Error Flag (OFF_Y) X-Axis Offset Error Flag (OFF_X)
The offset error flags are set if the associated signal reaches the specified offset limit. These flags may be cleared by writing a logic `1' value to the CE bit in DEVCTL. Offset faults are not reported for 1.5 seconds following reset. 3.1.3.8 Device Reset Flag (DEVRES)
This flag is set during device initialization. A logic `1' must be written to the CE bit in the Device Control register (DEVCTL) to clear this bit.
3.1.4
Counter Register (COUNT)
This read-only register provides the value of a free-running 8-bit counter derived from the primary oscillator. A five-bit prescaler divides the 4 MHz primary oscillator frequency by 32. Thus, the value in the register increases by one count every 8 s, and the counter rolls over every 2.048 ms. Table 3-6 Counter Register
Location Address $11 Register COUNT 7 COUNT[7] 6 COUNT[6] 5 COUNT[5] Bit Function 4 COUNT[4] 3 COUNT[3] 2 COUNT[2] 1 COUNT[1] 0 COUNT[0]
MMA6222EG 18 Sensors Freescale Semiconductor
SECTION 4 SERIAL COMMUNICATIONS
Digital data communication with MMA62XXEG is completed through synchronous serial transfers via the SPI port. Conventional SPI protocol is employed, with MMA62XXEG acting as a slave device observing CPOL = 0, CPHA = 0, MSB first. A number of data integrity features are incorporated into the transfer protocol.
4.1
4.1.1
SPI PROTOCOL
Overview
Each transfer is completed through a sequence of two operations, termed phases. During the first phase, the type of transfer and associated control information is transmitted from the SPI master to MMA62XXEG. Data from MMA62XXEG is transmitted during the second phase. Single-level queuing is employed as illustrated in Figure 4-1.
SCLK CS DIN Phase One: Type and Control
Request Error DOUT Request Error only reported on first access following reset Figure 4-1 Transfer Phase Detail
Phase Two: Data
Any activity on DIN or SCLK is ignored when CS is negated. Consequently, intermediate transfers involving other SPI devices may occur between Phase One and Phase Two.
SCLK CS DIN T1P1 T2P1 T3P1
T1P2 DOUT
T2P2
T3P2
Figure 4-2 Single-Level Communications Queuing Detail
MMA6222EG Sensors Freescale Semiconductor 19
The first data transmitted by MMA62XXEG following reset is the Request Error message shown below. This occurs because MMA62XXEG transmits during Phase Two and there is no corresponding Phase One for the first transfer.
BIT SCLK CS DOUT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
P
1
1
1
0
0
0
0
0
0
0
RE
0
Figure 4-3 Request Error Frame
4.1.2
Command Format
The following abbreviations are used in the following figures.
Bit Address Bit Name A[4:0] D[9:0] Acc AXIS P S[1:0] Register address 10-bit acceleration data Acceleration data indicator Axis specifier Parity Status Description DIN 12:8 N/A 13 14 N/A N/A DOUT 12:8 9:0 13 14 12 11:10
Commands are transferred from the SPI master to MMA62XXEG. Commands fall into three categories: acceleration data requests, register operations and device test. Acceleration data requests are initiated when bit 13 from the master is set to a logic `1' state. Register operations and device test are when bit 13 is set to logic'0' and are further distinguished by the states of bits 15 and 14.
4.1.3
Acceleration Data Transfers
Acceleration data requests are initiated when bit 15 from the master is set to a logic `0' state and bit 13 is set to a logic `1' state. The axis associated with the acceleration to be transferred is determined by DIN bit 14.
BIT SCLK CS DIN 0 AXIS Acc X X X X X X X X X X X X X 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Figure 4-4 Acceleration Command Format
MMA6222EG 20 Sensors Freescale Semiconductor
Acceleration data is returned as illustrated below. In addition to the acceleration value, the axis associated with the measurement is indicated in bit 13, while bits 11 and 10 provide status information.
BIT SCLK CS DOUT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
AXIS
P
S1
S0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 4-5 Acceleration Command Response
BIT SCLK CS DOUT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
AXIS
P
S1
S0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 4-6 Acceleration Command Response, Self-Test Active
4.1.4
AXIS Bit
Bit 13 indicates the axis associated with acceleration data, as shown below. Table 4-1 AXIS Bit Definitions
AXIS 0 1 Selected Axis X Y
4.1.5
Status Bits
Data bits 11 and 10 convey additional information regarding the acceleration data being transmitted. If an error condition is indicated, bits D9 through D0 contain flags which further describe the nature of the error. Table 4-2 STATUS Bit Definitions
Status Bit Definition S1 0 0 1 1 S0 0 1 0 1 Not Applicable Acceleration Data Self-test Data Error
The combination S1 = 0, S0 = 0 is never transmitted by MMA62XXEG in response to an acceleration data command.
MMA6222EG Sensors Freescale Semiconductor 21
4.1.6
Acceleration Response Error Status
Several error conditions may be detected and reported in response to an acceleration data command.
BIT SCLK CS DOUT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
AXIS
P
1
1
0
0
0
0
0
ND
0
HE
0
0
Figure 4-7 ND/HE Error Frame 4.1.6.1 ND - No Data Available
Bit 4 will be set to indicate a "No Data" condition if acceleration data is requested while the device is undergoing device initialization following reset. To ensure that an unexpected device reset will always be detectable regardless of the interval at which the sensor is accessed, "No Data" status will be returned in response to the first acceleration data request following device initialization. 4.1.6.2 * * * HE - Hardware Error Device over-temperature Offset error Internal parity error
A fault has been detected within the MMA62XXEG device. Detectable fault conditions are listed below
Specific error conditions are indicated in the device status register. The contents of this register are returned in response to a device test operation, as described in Section 4.1.10. Oscillator fault status will be reported only if the internal oscillator is functional but frequency comparison between the primary and reference oscillators fails. If an oscillator fault condition exists, the device will respond as described in Section 4.2.2.2. 4.1.6.3 CNC - Conditions Not Correct
Acceleration data will not be provided when bit 15 of command is detected as logic `1'. The response to such requests is illustrated below. Should a No Data Available or Hardware Error condition also exist, it will be reported as well.
BIT SCLK CS DOUT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
AXIS
P
1
1
0
0
0
0
0
ND
1
HE
0
0
Figure 4-8 CNC Error Frame
4.1.7
Non-Acceleration Transfers
Three different types of non-acceleration transfers are supported; register write, register read and device test. Non-acceleration data transfers are initiated when bit 13 from the master is set to a logic `0' state. The operation to be performed is indicated by bits 15 and 14. Table 4-3 Non-Acceleration Operations
Bit 15 0 0 1 1 Bit 14 0 1 0 1 Operation Unused Register Write Register Read Device Test
MMA6222EG 22 Sensors Freescale Semiconductor
Non-acceleration transfers will always succeed except in the case of oscillator fault, SPI error or request error conditions. Only oscillator failure, SPI error or request error conditions are reported in response to non-acceleration commands. Other error condition are reported as hardware errors in response to acceleration data requests.
4.1.8
Register Write Operations
Register write operations are initiated when bits 15 and 13 from the master is set to a logic `0' and bit 14 is set to a logic `1'. Bits 12 through 8 contain a five-bit address, while the last eight bits contain the data value to be written. Only the DEVCTL register is writable. If an attempt is made to write to any register other than DEVCTL, a request error response (see Figure 4-15) will occur.
BIT SCLK CS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN
0
1
0
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Figure 4-9 Register Write Command Response to a register write operation is illustrated below. DEVCTL bits which can be read as logic `1' (HPFB, ST1 and ST0) will be indicated during the last eight clock cycles, as shown.
BIT SCLK CS DOUT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
1
P
1
1
1
0
0
0
0
0
HPFB
0
ST1
ST0
Figure 4-10 Register Write Command Response
4.1.9
Register Read Operations
Register read operations are initiated when bit 15 from the master is set to a logic `1' state and bits 14 and 13 are driven to a logic low level. The address of the register to be accessed is contained in bits 12 through 8. DIN bits 7 through 0 are ignored by MMA62XXEG during register read command transfers.
BIT SCLK CS
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DIN
1
0
0
A4
A3
A2
A1
A0
X
X
X
X
X
X
X
X
Figure 4-11 Register Read Command Data read from the selected register is returned in bits 7 through 0, as shown below.
BIT SCLK CS DOUT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
0
P
1
1
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Figure 4-12 Register Read Command Response
MMA6222EG Sensors Freescale Semiconductor 23
4.1.10
Device Test Operation
A device test operation is conducted when DIN bits 15 and 14 are at a logic high level and bit 13 is driven to a logic low level.
BIT SCLK CS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN
1
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
Figure 4-13 Device Test Command The content of the device status register are transmitted in bits D7 through D0 in response to a device test operation. Refer to Section 3.1.3 for details regarding the device status register
BIT SCLK CS DOUT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
1
P
1
1
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Figure 4-14 Device Test Command Response Status register bit 0 is set following any device reset. This bit will remain set until explicitly cleared by writing the CE bit in the device control register, as described in Section 3.1.1.
4.1.11
Non-Acceleration Request Error
An error condition is indicated if a non-acceleration command is detected and DIN bits 15 and 14 are both zero, as no operation is specified for this combination.
BIT SCLK CS DOUT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
P
1
1
1
0
0
0
0
0
0
0
1
0
Figure 4-15 Non-Acceleration Request Error
4.1.12
SPI Error Response
The following conditions detected at DIN will result in a SPI error. Since the error condition likely indicate a corrupted transfer, the response frame is the same regardless of the state of bit 13 at DIN. * * * * SCLK high when CS asserted Fewer than 16 rising edges of SCLK detected while CS is asserted Greater than 16 rising edges of SCLK detected while CS is asserted SCLK high when CS negated
MMA6222EG 24 Sensors Freescale Semiconductor
The response to a SPI error condition is shown below.
BIT SCLK CS DOUT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
P
1
1
1
0
0
0
0
0
0
1
0
0
Figure 4-16 SPI Error Response
4.1.13
Initial Response
During initialization phase one, the device does not respond to SPI access attempts. During the second initialization phase, register operations complete normally, however the device will respond to sensor data requests with No Data (ND) status. The first acceleration request following completion of device initialization will also result in a No Data response. This ensures that an unexpected reset will always be detectable, even in systems which poll the device at longer intervals than required for device initialization.
4.2
ERROR CONDITIONS
A number of error conditions may be detected. If an error condition is detected, MMA62XXEG will always transmit an error indicator in place of acceleration data. Error indicators are defined in the following sections.
4.2.1
Error Condition Classification
Error conditions fall into five classes, as described below. 4.2.1.1 Critical Errors
Error condition affects device operation. Critical errors are always reported regardless of other error conditions which may be detected. 4.2.1.2 Initialization
Initialization is a special case condition which occurs after reset until internal circuitry is ready to provide accurate acceleration results. The duration of the initialization period depends upon whether a high-pass filter has been selected or not. If no high-pass filter has been selected, initialization requires approximately 3 ms after power-up. If a high-pass filter has been selected, an additional 200 ms is required. During the device initialization period, this status is reported in response to any acceleration data request, however normal register access operations may be performed. Device initialization status is cleared automatically. 4.2.1.3 Reset
Reset is also a special case condition. Reset will occur at power-on, as the result of a temporary undervoltage condition, or in response to explicit actions taken by the controller. Upon negation of the internal reset signal, the DEVRES flag in the device status (DEVSTAT) register is set. Because it is critically important that the system can detect any unintended reset condition, this flag may only be cleared by writing a logic `1' to the CE bit in the device control register (DEVCTL) after device initialization has completed. 4.2.1.4 Transient Errors
An error condition which may be the result of a condition which precludes an accurate acceleration measurement but which may not persist. Transient errors are reported in response to acceleration data transfer requests. If a transient error condition has been detected, a logic `1' may be written to the clear error (CE) bit in the device control (DEVCTL) register to clear the associated flag. Should the error condition still exists, the flag will only be cleared momentarily.
MMA6222EG Sensors Freescale Semiconductor 25
4.2.1.5
External Errors
An error condition resulting from an invalid command input or corrupted data transfer. External errors are reported only once. Errors are prioritized as shown in the table. In the event that multiple error conditions are detected, the highest priority error will be reported.
4.2.2
4.2.2.1
Error Definitions
Internal Data Error
Class: Critical error A parity fault has been detected in the internal data registers. In the event of a soft error (bit-flip within the register), an internal data error may be recoverable by resetting the device. 4.2.2.2 Internal Oscillator Fault
Class: Critical error If an oscillator fault condition is detected, DOUT is driven high continuously when CS is asserted, as illustrated below.
SCLK CS DOUT
Figure 4-17 Oscillator Failure Response 4.2.2.3 Device Initialization
Class: Reset Following a reset condition, the device requires a period of time to complete initialization of the DSP and internal registers. If multiple SPI transfers are attempted during this initialization period, the second and all subsequent transfers will result in this status. The first transfer following reset, regardless of the state of initialization returns device reset status. 4.2.2.4 Temperature Fault
Class: Transient error The internal temperature sensor value exceeds the allowable limits for the device. 4.2.2.5 Unexpected Axis Selection
Class: External error An acceleration data request has been received with an axis specification which is not supported. 4.2.2.6 Offset Error
Class: Transient error This condition exists if the output of the offset monitor circuit reaches 10% of the full-scale value and the OFMON bit is set in the DSPCFG1 register. 4.2.2.7 Device Reset
Class: Reset Following any reset operation, the device returns this status during the first acceleration data access. 4.2.2.8 SPI Clock Fault
Class: External error A SPI clock fault may result from the following conditions: * * The number of rising clock edges detected while CS is asserted is not equal to 16 SCLK is high when CS is asserted
4.3
ACCELERATION DATA REPRESENTATION
Acceleration values may be determined from the 10-bit digital output (DV) as follows: MMA6222EG 26 Sensors Freescale Semiconductor
a = sensitivity x DV
(signed data representation)
Sensitivity is determined by nominal full-scale range (FSR), linear range of digital values and a scaling factor to compensate for sensitivity error. The linear range of digital values for MMA62XXEG is limited to accommodate overrange values produced by the DSP along with two reserved end values. The linear range of digital values and signed values is from -509 to +508. Note that the ranges are asymmetrical by 1 LSB. The sensitivity error scaling factor is determined as follows: scale_factor = (100.0 - error_tolerance) / 100.0 Finally, the nominal sensitivity in terms of acceleration per LSB is determined: 1 LSB = (FSR / scale_factor) / ((Max_Linear_Value - Min_Linear_Value) / 2.0); For the linear ranges of digital values indicated and projected sensitivity values, the nominal value of 1 LSB for each full-scale range is shown in the table below. Table 4-4 Nominal Sensitivity (10-bit data)
Full-Scale Range (g) 100 50 35 20 Nominal Sensitivity (g/digit) Sensitivity Error = 4% 0.2048 0.1024 0.07170 0.04097
MMA6222EG Sensors Freescale Semiconductor 27
Table 4-5 Nominal Signed Acceleration Data Values
Nominal Acceleration Digital Value 20 g 511 510 509 508 507 506 * * * 127 126 125 * * * 3 2 1 0 -1 -2 -3 * * * -126 -127 -128 * * * -507 -508 -509 -510 -511 -512 +20.8 +20.8 +20.7 * * * +5.20 +5.16 +5.12 * * * +0.123 +0.082 +0.041 0 -0.041 -0.082 -0.123 * * * -5.16 -5.20 -5.24 * * * -20.8 -20.8 -20.9 10-Bit Range (Self Test Disabled) 35 g Reserved Overflow Overrange +36.4 +36.4 +36.3 * * * 9.11+ +9.03 +8.96 * * * +0.215 +0.143 +0.072 0 -0.072 -0.143 -0.215 * * * -9.03 -9.11 -9.18 * * * -36.4 -36.4 -36.5 +52.0 +51.9 +51.8 * * * +13.0 +12.9 +12.8 * * * +0.307 +0.205 +0.102 0 -0.102 -0.205 -0.307 * * * -12.9 -13.0 -13.1 * * * -51.9 -52.0 -52.1 +104 +104 +104 * * * +26.0 +25.8 +25.6 * * * +0.614 +0.410 +0.205 0 -0.205 -0.410 -0.614 * * * -25.8 -26.0 -26.2 * * * -104 -104 -104 50 g 100 g
Underrange Underflow Reserved
MMA6222EG 28 Sensors Freescale Semiconductor
4.3.1
Overrange Response
Positive acceleration levels which exceed the full-scale range of the device fall into two categories: overrange and overflow. Overrange conditions exist when the signal level is beyond the full-scale range of the device but within the computational limits of the DSP. An overflow condition occurs if the output of the low-pass filter equals or exceeds the maximum digital value which can be output from the sinc filter. Sinc filter saturation will occur before the internal datapath width is exceeded. At 25C the sinc filter will not saturate at sustained acceleration levels with the range of 200 g. The DSP operates predictably under all cases of overrange, although the signal may include residual high frequency components for some time after returning to the normal range of operation due to non-linear effects of the sensor. If an overflow condition occurs, the signal is internally clipped. The DSP will recover from an overflow condition within a few sample times after the input signal returns to the input range of the DSP. Due to internal clipping within the DSP, some high-frequency artifacts may be present in the output following an overflow condition. For negative acceleration levels, corresponding underrange and underflow conditions are defined.
4.4
CAP/HOLD INPUT
The CAP/HOLD input provides a system-level synchronization mechanism. When driven high, transfer of acceleration results from the DSP to the SPI buffers does not occur. The DSP continues its normal operation regardless of the state of CAP/HOLD. Data read from the device when CAP/HOLD is high will reflect the last values available from the DSP at the time of the signal transition.
MMA6222EG Sensors Freescale Semiconductor 29
SECTION 5 OPERATING MODES
MMA62XXEG operates in one of two modes, factory test programming mode and normal operating mode. Factory test and programming mode is entered only when certain conditions are met, and provides support for programming of customer-defined data. Normal mode is entered by default when the device is powered on.
5.1
NORMAL OPERATING MODE
Normal mode is entered whenever the device is powered and the VPP pin is held at or below the level of VCC. In normal mode, acceleration data and device support data transfers are supported.
5.1.1
Power-On Reset
Upon application of voltage at the VCC pin, the internal regulators will begin driving the internal power supply rails. The CREG and CREGA pins are tied to the internal rails. As voltages at VCC, CREG and CREGA rise, the device becomes operational. An internal reset signal is asserted at this time. Separate comparators on monitor all three voltages, and when all are above specified thresholds, the reset signal is negated and the device begins its initialization process.
5.1.2
Device Initialization
Following any reset, the device completes a sequence of operations which initialize internal circuitry. Device initialization is completed in two phases. During the first phase, the fuse array is read and its contents are transferred to mirror registers. Power to the fuse array is then removed to reduce supply current load. A voltage reference used within the sensor interface stabilizes during the second phase. If the HPFSEL bit is set in the DSP configuration register (DSPCFG), the high-pass filter is also initialized during phase two. The device will not respond to SPI accesses during initialization phase one. Acceleration results are not available during initialization phase two, however the SPI is functional and register operations may be performed. If an acceleration data access is attempted, the device will respond with non-acceleration data. The first initialization phase requires approximately 800 s to complete. The second phase completes in approximately 3 ms if no high-pass filter is selected, and 200 ms if the HPFSEL bit is programmed to a logic `1' state. The DEVINIT bit in the device status register (DEVSTAT) remains set following reset until the second phase of device initialization completes.
MMA6222EG 30 Sensors Freescale Semiconductor
APPENDIX A
Table A-1: Low-Pass Filter Options
Filter Option LPF_X[4] LPF_Y[4] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LPF_X[3] LPF_Y[3] 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 LPF_X[2] LPF_Y[2] 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 LPF_X[1] LPF_Y[1] 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 LPF_X[0] LPF_Y[0] 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Reference 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Cutoff Frequency fC (HZ) 10 15 30 50 75 100 130 160 200 250 300 350 400 500 600 700 800 900 1000 10 15 30 50 75 100 130 160 200 250 300 350 400 2 16 32 64 4 16 32 Equivalent Poles Sample Time tS s 256 128 64
MMA6222EG Sensors Freescale Semiconductor 31
PACKAGE DIMENSIONS
MMA6222EG 32 Sensors Freescale Semiconductor
PACKAGE DIMENSIONS
MMA6222EG Sensors Freescale Semiconductor 33
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